# Digital Logic Gate Delays

In digital logic, the poor timing of events can be the difference between a glitch and proper execution. The signals in the circuit must pass through the MOSFETs P and N regions of the logic gates to execute whatever it is your circuit is accomplishing. While in a copper wire, the speed of the electrons is about 0.59c to 0.77c with c being the speed of light at c = 299,792,458 m/s. That’s between 176,877,550 and 230,840,192 m/s or 395,663,810 and 516,374,803 mph. That’s really fast. So fast that it’s nearly impossible to visualize that speed. Here’s a neat map visualizer for how long it takes to get anywhere in the world https://academo.org/demos/speed-of-light-visualizer/

So, with each MOSFET that your signal passes through, there is a delay of that electric signal. No longer moving at the near speed of light velocities seen before. Each different type of logic gate has a different number of MOSFETs which leads to different delays in the signal. To the left is a table of the different delays involved with the various gates used in digital logic design. The table describes that signals are slowed on the picosecond magnitude, so it is small but not insignificant when taking about over half the speed of light velocities.

You’ll notice two columns with different times listed. Propagation Delay and Contamination Delay. These two times give the worst-case scenario time and the best-case scenario respectively.

If you are building a sequential circuit, where the timing of signals is essential, you must keep the worst-case times of your circuit in mind.

All this text about the delay caused by digital logic circuits is due to a neat project that was mentioned in the textbook of my ECE 271: Digital Logic Design textbook. The circuit depicted is called Ring Oscillator. It is a simple line of NOT gate in a loop. It is important that there is an odd number of NOT gates in the circuit so that the last NOT gate in the loop sends out the inverse of the original signal. When that signal loops back around to the input of the first NOT gate it will invert again once it passes through the last gate, returning to the original signal. The process loops and continues, switching between a logic 1 and a logic 0, making an oscillation.

The equation for the frequency of a ring oscillator is described as f = 1/2π*N*td where N is the number of NOT gates (must be odd) and td is the time delay of your circuit.

Article last edited: August 2021